If you own a Huawei phone or have been following the global chip race from Malaysia, the company has just spelled out how it plans to keep making its processors faster without leaning on the ever-shrinking transistors that have driven the industry for decades. At a major engineering conference this week, Huawei introduced what it calls the Tau Scaling Law, a different way of thinking about how chips improve.
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What the Tau Scaling Law is
At the 2026 IEEE International Symposium on Circuits and Systems in Shanghai, Huawei executive He Tingbo gave a keynote called "New Semiconductor Path in Practice" and presented the Tau (τ) Scaling Law. The idea is to stop treating ever-smaller transistors as the main measure of progress, and instead focus on cutting the time it takes for signals to travel through a chip and the wider system. Huawei frames this as a shift from geometric scaling to time scaling.
To put the principle into practice, Huawei has built a technique it calls LogicFolding. According to the company, it rearranges circuits to shorten the wiring that signals must cross, which raises how densely transistors can be packed and how efficiently they run. Huawei says the approach works across four levels: the device, the circuit, the chip, and the full system, where a new interconnect it calls UnifiedBus reduces communication delay.
Why it matters
Moore's Law, the long-standing rule of thumb that transistor counts roughly double every couple of years, has been slowing as the physics gets harder and the cost per transistor stops falling. Huawei's argument is that you can keep improving performance and efficiency by attacking delay at every layer rather than chasing a smaller manufacturing node. That matters for Huawei in particular, because US export controls have limited its access to the most advanced chipmaking equipment, so squeezing more out of existing process nodes is a way around part of that wall.
The figures Huawei shared are notable, though they are the company's own claims and have not been independently verified. Huawei says LogicFolding lifts transistor density on its 2026 Kirin chips by about 53.5 percent, to as much as 238 million transistors per square millimetre, alongside a 40 percent gain in performance-core power efficiency and a peak clock of around 3.1GHz. It also says it has designed and mass-produced 381 chips based on the Tau Scaling Law over the past six years.
What it means for devices
The most direct consumer angle is phones. Huawei says the Kirin chips launching in Fall 2026 will be the first to use the LogicFolding architecture, which should translate into better performance and battery life in its flagship devices. Looking further out, the company expects high-end chips built on the Tau Scaling Law to reach transistor density equivalent to a 1.4nm process by 2031, a level that today only the leading foundries are targeting.
For Malaysian buyers, none of this changes what is on shelves right now, and Huawei has not tied any specific local launch to the announcement. But it points to the direction of the Kirin chips that sit inside the Huawei phones, tablets, and wearables sold here.
The takeaway
Huawei is making a wider case that the chip industry needs a new yardstick, and it is holding up its own engineering as evidence that progress can continue without the newest factories. He Tingbo closed by calling for more openness and collaboration across the industry. Whether the Tau Scaling Law catches on beyond Huawei will come down to results, but the company has at least given the post-Moore debate a concrete plan to argue over.